An Energy-Efficient Time-Domain Analog CMOS BinaryConnect Neural Network Processor Based on a Pulse-Width Modulation Approach

This paper proposes a time-domain analog calculations model based on pulse-width modulation (PWM) approach for neural network including weighted-sum or multiply-and-accumulate calculation and rectified-linear unit operation. We also propose very-large-scale integration (VLSI) circuits to implement the proposed model. Unlike conventional voltage current mode circuits, our use transient operation in charging/discharging processes capacitors through resistors. Since calculate multiple weighted-sums by charging capacitance, they can be operated with extremely low energy consumption. However, because relatively long time constant is required guarantee resolution domain, have very high-resistance devices, order of giga-ohms. designed, fabricated, tested proof-of-concept complementary metal-oxide-semiconductor (CMOS) VLSI chip using 250-nm fabrication technology verify binary weights PWM input signals, which realizes BinaryConnect In chip, memory cells static-random-access (SRAM) are used synaptic connection weights. High-resistance was realized subthreshold region MOS transistors, unlike ordinary in-memory-computing circuits. evaluated efficiency temperature characteristics measurement fabricated where highest 300 TOPS/W (Tera-Operations Per Second per Watt). The effects change compensated adjusting bias voltage. If state-of-the-art model, an more than 1,000 will possible.